//l_1 vale 1 para indicar la operacion de cargar el multiplicando. l_2, para
//la operacion del multiplicador. on indica que la maquina puede partir
//multiplicando
module controlUnit_init(G, Z,clk,reset, on, l_1, l_2);
input G, clk, reset, Z;
output reg on;
reg [1:0] state, nextstate;
reg [1:0] Csignal;
output l_1, l_2;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b11;
parameter S3 = 2'b10;

always @(posedge clk)
if(reset) state <= S0;
else state <= nextstate;

always @(*)
begin
case(state)
S0: if(G) begin nextstate = S1; Csignal = 2'b10;end
    else  begin nextstate = S0;Csignal = 2'b00;end
S1: if(G) begin nextstate = S1; Csignal = 2'b00;end
    else  begin nextstate = S2; Csignal = 2'b00;end
S2: if(G) begin nextstate = S3; Csignal = 2'b01;end
    else  begin nextstate = S2; Csignal = 2'b00;end
endcase
if (state == S3)
    begin
        if (Z) nextstate = S0;
        on=1; 
        Csignal = 2'b00; 
        end 
        else on=0;
    end
assign {l_1,l_2} = Csignal;
endmodule

module controlUnit # (parameter N=4)(Q, Z, G, reset, clk, Csignal);
    parameter S0 = 0;
    parameter S1 = 1;
    input G, clk, reset, Q, Z;
    wire enable;
    wire l_1, l_2;
    reg state, nextstate;
    wire rst;
    controlUnit_init cin(G ,Z, clk, reset, enable, l_1, l_2);

    reg load_counter, load_B, load_Q, reset_A, reset_C;

    //100: Solo hacer shift de C->A->Q. 101: Shift + Load de la salida del
    //pararell adder en A. 011: cargar multiplicando. 010: cargar
    //multiplicador. 000: Stand by
    output reg [2:0] Csignal;
    always @ (posedge clk)
    begin
        if (enable&~Z) state <= S1; else state <= S0;
    end


    always @ (*)
    begin
        if (state == S0)
            Csignal = {1'b0,l_1|l_2,l_1};
        else
        begin
        if (Q == 0)
                Csignal = 3'b100;
            else
                Csignal = 3'b101;
        end
    end
endmodule
